The present invention relates to a random access memory provided with a back-gate bias circuit.
Generally, it is known that it is effective to apply a back-gate bias voltage to a substrate for realization of a high operating speed of an integrated circuit of the MOS type, in particular, an n-channel type MOS integrated circuit. The following effects are obtained due to the application of the back-gate bias voltage.
(i) A depletion layer in the junction between the substrate and the active region extends, so that the junction capacitance is reduced.
(ii) The impurity concentration of the channel stopper can be reduced since the threshold value of a parasitic MOS transistor increases, so that the junction capacitance between the active region and the substrate can be decreased.
(iii) The substrate effect to the threshold value of the MOS transistor can be suppressed.
FIG. 1 shows a back-gate bias circuit which is formed in a substrate and generates a substrate bias voltage VB. This back-gate bias circuit comprises a ring oscillator 1 and a charge pump circuit 2 for applying back-gate bias voltage VB to the substrate in response to an output signal of ring oscillator 1. Charge pump circuit 2 has a capacitor C, one end of which is connected to ring oscillator 1 and n-channel MOS transistors Q.sub.1 and Q.sub.2, which are connected in series between a substrate terminal ST and the ground, and a connecting point of which is coupled with the other end of capacitor C. Gates of MOS transistors Q.sub.1 and Q.sub.2 are connected to substrate terminal ST and the connecting point, respectively.
The substrate potential or back-gate bias voltage VB is determined by the relation between a current which is supplied from the back-gate bias circuit to the substrate and a substrate current flowing through the substrate when for example, a memory circuit formed on the same substrate as the back-gate bias circuit operates. Although the current supply capability of the back-gate bias circuit increases in proportion to a power source voltage VC, the substrate current flowing through the substrate when the memory circuit operates exponentially increases with the increase in the power source voltage. Therefore, although back-gate bias voltage VB rises until power source voltage VC reaches a predetermined level (about 6 V) as shown in FIG. 2, when voltage VB becomes higher than voltage level VC, it suddenly decreases.
The back-gate bias circuit provided in a memory circuit such as RAM is designed so as to generate a stable substrate bias voltage for the whole operating range of the power source voltage which is required to drive the memory circuit. Therefore, in the conventional device technology, a bias voltage larger than a reference potential (ground potential) is applied to the whole substrate of the chip.
FIG. 3 shows a cross sectional structure of an n-channel MOS transistor, constituting one of the memory cells in the conventional RAM. This MOS transistor comprises n.sup.+ -type source and drain regions 4S and 4D formed in the surface area of a p-type silicon substrate 3; and a gate region 5 formed on the channel region between source and drain regions 4S and 4D.
FIG. 4 shows a static memory cell including MOS transistors Q.sub.3 and Q.sub.4 constituted similarly to the MOS transistor shown in FIG. 3. One end of each of MOS transistors Q.sub.3 and Q.sub.4 is grounded and their other ends are coupled with a power source terminal VC through resistors R.sub.1 and R.sub.2, respectively. A node N.sub.1 between resistor R.sub.1 and MOS transistor Q.sub.3 is connected to a gate of MOS transistor Q.sub.4 and is also connected through a MOS transistor Q.sub.5 to a bit line BL.sub.0. A node N.sub.2 between resistor R.sub.2 and MOS transistor Q.sub.4 is connected to a gate of MOS transistor Q.sub.3 and is also connected through a MOS transistor Q.sub.6 to a bit line BL.sub.1. Gates of MOS transistors Q.sub.5 and Q.sub.6 are connected to a word line WL. In FIG. 3, a polysilicon layer 6 formed on drain region 4D and an insulating layer 7 constitutes the line between node N.sub.1 and the gate of MOS transistor Q.sub.4 in FIG. 4.
Generally, in the MOS integrated circuit, a crystal defect may occur in silicon substrate 3 in the manufacturing process. As indicated by a point DP in FIG. 3, the crystal defect may be formed in substrate 3 at a position near the junction between substrate 3 and n.sup.+ -type region 4D. For example, in the case where crystal defect DP is formed at the position in the substrate corresponding to node N.sub.1 in a memory cell in the static RAM shown in FIG. 4, the data stored in this memory cell may be destroyed for the following reasons. The potential at node N.sub.1 is held at the ground level or power source voltage level when data of "0" or "1" is stored into the memory cell. For instance, the case where power source voltage VC increases in the state in which the potential at node N.sub.1 is held at the "1" level will now be considered. In such a case, a higher reverse bias voltage is applied between substrate 3 and n.sup.+ -type region 4, so that the depletion layer in the junction therebetween may enlarge and reach crystal defect DP. When the depletion layer has reached crystal defect DP in this manner, a leakage current from node N.sub.1 to substrate 3 suddenly increases, so that the potential at node N.sub.1 decreases. With the reduction in the potential at node N.sub.1, the potential at node N.sub.2 rises and destroys the data in the memory cell. The back-gate bias circuit is driven by the power source voltage for driving the memory and supplies a fairly deep substrate bias voltage to the substrate within a variation range of the power source voltage for driving the memory. Therefore, in this case, there is the possibility such that the memory data is broken for the foregoing reasons.